Promotion gates

A device recipe moves through four explicit states.

State	Meaning
exploratory	equations or implementation are still changing; no optimization claim
experimental	reproducible offline branch and observables; FDTD direction not established
validation	at least one direction confirmation; remaining audits are named
supported	all gates pass on immutable fixtures with pinned tolerances

Gates for supported status

1. Analytical basis, contour, and truncation convergence for the benchmark.
2. Implicit pole and observable gradients agree with centered finite differences over representative coordinates and random directions.
3. Two consecutive, independent analytical-to-FDTD direction confirmations.
4. FDTD grid, duration, monitor-downsampling, domain, and mode-port convergence.
5. Stable branch overlap throughout the allowed trust radius.
6. Observable definitions and loss closure pass schema-level diagnostics.
7. Simulation serialization works with the supported Tidy3D version.
8. Benchmark input, raw provenance, extracted record, and tolerance are frozen.

A gate may be marked not applicable only with a documented physical reason. Historical success in a different material stack or objective does not satisfy a gate.

For mode-resolved FDTD beta, gate 4 includes signed six-face loss closure, nested flux-box agreement, direct mode-field branch identification, incoming power, all-propagating-mode closure, direct-power versus Q-ratio agreement, time-window sensitivity, and explicit treatment of any symmetry inference. See FDTD verification.