Technical note charge depletion

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Here’s a concise recap of the key points we’ve covered:

  1. Why a depletion diode (or MOS stack) is needed

Screening by mobile carriers: In a semiconductor, any applied field is immediately shorted by free electrons/holes unless you first deplete them out.

Uniform, blockable field: A reverse-biased p–i–n or MOS capacitor creates an intrinsic (depleted) region where a clean electric field can be held without leakage.

Deterministic charge control: Tunnel-in/out from doped contacts lets you load single electrons (or holes) into your dot and hold them there—impossible with bare electrodes.

  1. Why simply gating an insulator isn’t enough

Lack of a carrier reservoir: An insulator has no conduction path, so you can’t “sweep away” trapped or residual charges.

Deep trap binding: Bound charges live in eV-deep defect levels; fields of ∼1 MV/m only shift potentials by meV over atomic distances, far too small to ionize them.

Breakdown limits: Insulators typically avalanche at 10⁷–10⁸ V/m, so you can’t safely crank the field high enough to force ionization.

  1. Stabilizing DBT in anthracene

  2. Material quality & growth

Zone-refined anthracene, slow cooling, vacuum-grown crystals.

Encapsulation immediately after growth (e.g. hBN or ALD oxide).

  1. Electrical stabilization

Embed in a MOS-capacitor (SiO₂/anthracene/Al₂O₃ stack with top metal gate and n⁺-Si back contact).

Reverse-bias pulses to clear interface and trap charges, then hold a static Stark field.

Optional real-time Stark-feedback loop (measure ZPL shifts and adjust gate).

  1. Cryogenics & shielding

Lower T (1.5–4 K) to slow TLS.

RF/magnetic shielding and filtered wiring to suppress external noise.

  1. Passive passivation

Conformal ALD Al₂O₃ (5–10 nm) to neutralize surface traps and provide a uniform dielectric.

Polymer or amorphous capping layers as an extra buffer.

  1. Active feedback (“spectral locking”)

Rapid ZPL scans + PID control to compensate slow drifts or jumps.

  1. The role of ALD Al₂O₃ encapsulation

Conformal, pinhole-free coverage over all exposed crystal faces (including sidewalls).

Chemical passivation of dangling bonds and adsorbates by forming stable Al–O bonds.

Uniform dielectric environment (εᵣ≈9) that smooths local field inhomogeneities.

Controlled tunneling barrier (5–10 nm) for trap evacuation under reverse bias without high leakage at operating voltages.

  1. Building and operating your MOS-capacitor

Layer stack:

  1. n⁺-Si wafer (back contact)

  2. 200 nm SiO₂ gate oxide

  3. 100–200 nm DBT:anthracene film

  4. 5–10 nm ALD Al₂O₃ passivation

  5. Semi-transparent Ti/Au top gate

Operation:

Pulse reverse bias (e.g. –5 to –10 V) to tunnel-clear traps.

Step back to working bias (0–1 MV/m) for stable Stark tuning.

Repeat pulses on demand if spectral jumps reappear.

  1. Why lateral gold contacts aren’t enough

No depletion path → trapped charges remain and screen the field.

Non-uniform fringing fields → different dots see different Stark shifts.

Poor leakage control → either no trap evacuation or crystal damage.

Interface traps from metal islands → more noise, not less.

  1. Coating both faces with ALD

Flip-and-coat: ALD top, peel & flip crystal, ALD bottom.

Suspended-film ALD: Mount on mesh or grid so both faces are exposed.

Sacrificial layer peel: Float crystal on water over a support, coat both sides, then remove polymer.

  1. The danger of exceeding breakdown

Permanent pinholes & shorts in the oxide → loss of gate control.

Local joule heating → cracking or carbonizing the anthracene and destroying emitters.

New defect creation → more traps and worse spectral diffusion.

Putting all these pieces together—high-quality growth, conformal ALD passivation, a vertical MOS-cap structure, and controlled biasing and feedback—you can reduce DBT’s spectral diffusion from hundreds of MHz down to single-digit MHz or better and eliminate random jumps.