Inverse-design fidelity audit#

Fail-closed parity

A high optimizer scalar is not equivalence when the local scene changes the initialization, controls, symmetry, constraints, frequency samples, or FOM. The suite fails closed on those differences. Independent Tidy3D forward solves of the final binary artifacts withdrew two apparent local passes and confirmed only the S-matrix crossing within the user’s 10% trust target. Its 93.75% published-performance ratio still misses the repository’s 95% gate. Two unsupported large problems remain explicit exclusions instead of being replaced with easier compact surrogates.

Current disposition#

Tidy3D notebook

Published controls and start

Required symmetry / constraints

Current status

Autograd24 digital splitter

20×10 shallow-hole permittivities; uniform ε=6.5

electric y symmetry; published update and fabrication-radius sweep; upper-port five-wavelength FOM

Fails external validation: local 0.43253, but Tidy3D scores the same binary geometry 0.31384 versus 0.47210 published

Autograd8 bend

60 angular width controls; midpoint-width start

minimum-curvature penalty

Invalid: local adapter used unrelated 16×16 topology density

Autograd25 crossing

300×300 at 10 nm; published plus-cross start

one-eighth material symmetry; (0,-1,1) field symmetry; β=∞

Invalid: local adapter used 16×16, β=4, and no field symmetry

Autograd27 S-matrix

451×451 at 10 nm; published plus-cross start

exact D4 material symmetry; β=30; binary final projection

Passes 10%, misses 95%: Tidy3D same-geometry 0.91920 versus 0.98044 published (93.75%)

Autograd9 WDM

300×300; uniform 0.5; 20 frequency samples

100 nm conic filter; β 1→50; erosion/dilation; binary final projection

Invalidated: local 0.93813, but Tidy3D scores the same artifact 0.02938

Autograd17 bandpass

640×320; uniform 0.5; 51 frequency samples

120 nm conic filter; β 1→50; erosion/dilation; binary final projection

Fails strict parity: local 0.91277; Tidy3D same-geometry 0.73536 versus 0.82519 published

Autograd6 compact grating coupler

216×108 half-domain at 20 nm; random Gaussian-smoothed cold start

electric y symmetry; double constant-padded 80 nm filter; erosion/dilation; β 1→30; binary final projection

Fails: FDTDX 0.57728; Tidy3D same-geometry 0.53388 versus 0.66374 published

The detailed evidence, normalization derivation, and GPU memory measurements are maintained in docs/INVDES_AUDIT.md.

The executed Autograd24 splitter and Autograd6 grating-coupler audit notebooks show the full parameter → geometry → optimization → fresh validation → field-profile workflow. Their plots show the realized binary geometry and actual Yee-grid material, not merely optimizer controls.

Separate local fitted-Q validation#

The high-Q nanobeam notebook is not entered in the table above because it does not claim parity with a published Tidy3D inverse-design notebook. It validates a solver capability: automatic mirror completion, a JAX multi-window pole fit, exact-checkpointed FDTD gradients, bounded symmetric cylinder controls, and independent long-run validation of the final literal geometry. One cold-start adjoint update reaches Q=187,133, which is 5.33× the unchanged cavity and 2.02× the unoptimized mirror-completed control, with zero fabrication violation. A separately billed matched Tidy3D pair uses 20 literal holes for both the control and final shape: Q increases from 84,247 to 146,678, or 1.741×. This confirms a real shape-only gain while showing that the 25 nm FDTDX model overpredicts its magnitude.

Independent forward sign-off#

The final-design checks use no Tidy3D optimization. Each FDTDX binary artifact is inserted into the source notebook’s exact Tidy3D forward scene and scored with the published observable.

design

FDTDX claim

Tidy3D same geometry

published Tidy3D

disposition

WDM

0.93813

0.02938

0.82566

invalid local objective/normalization

bandpass

0.91277

0.73536

0.82519

10.9% below published; strict gate fails

digital splitter

0.43253

0.31384

0.47210

33.5% below published

S-matrix crossing

0.96945

0.91920

0.98044

10% trust check passes; 95% gate fails

compact grating coupler

0.57728

0.53388

0.66374

within 8.1% cross-solver, but 19.6% below published

The grating comparison uses the executed notebook result of −1.78 dB (0.663743). The nearby prose still says 150 iterations and −1.48 dB, but that text is stale relative to the retained 75-step execution and final spectrum.

The splitter FOM error#

The Autograd24 notebook’s upper-port objective is bounded by 0.5. Tidy3D multiplies it by two only for total insertion loss. Because FDTDX normalizes the source on the reduced half-plane, the physical upper-port value is

\[ T_\mathrm{upper}=\frac{1}{2}\frac{P_\mathrm{upper,reduced}}{P_\mathrm{source,reduced}}. \]

The old adapter omitted the factor \(1/2\) and called 0.752 a win. It was about 0.376 under the notebook convention, below the 0.4485 requirement. The corrected benchmark also records total transmission and source drift, so this mistake cannot silently return.

Why the refined mesh is still coarse#

The notebook’s automatic mesh targets roughly 22.4 nm inside silicon. On the local RTX 3080 12 GB, the selected 45 nm xy / 50 nm z grid has an 8.70 GiB raw PML tape before reverse workspace. The automatic recorder chooses float16 storage with every-fourth-step reconstruction, reducing the tape to 1.09 GiB inside its 1.22 GiB budget; the complete adjoint uses about 9.2 GB on device. Eight-by-eight hole quadrature and exact planar-interface alignment give a cold start of 0.12245 versus Tidy3D’s 0.1113.

This is a real device-memory limitation, not a justification for comparing a different optimization problem. Feature-aware spacing, physical-PML retention, interface alignment, and recorder-memory planning are now automatic. Local refinement around the slab and holes remains the next memory-efficiency step.

Memory-feasible scope#

The digital splitter, WDM, bandpass, S-matrix crossing, and compact grating coupler are memory-feasible on this machine. The grating retains all 216×108 20 nm controls; its 125×63×94 reduced Yee grid uses about 9.2 GiB on the GPU, with a 0.96 GiB planned reversible tape. Autograd8’s published 10×10×3.7 µm bend would require an approximately 30 GiB raw reverse tape plus a differentiable polygon/curvature rasterizer that FDTDX does not yet have. Autograd25’s 10 nm, 1.67 ps crossing would require hundreds of GiB even after its y/z field symmetries. Those two cases therefore stay excluded instead of being represented by unrelated 16×16 topology problems.

Restore criteria#

  • the same start—never an unpublished warm start;

  • the same parameters, filter/projection schedule, symmetries, and fabrication constraints;

  • the same physical FOM and normalization, with separate passivity checks;

  • geometry plus multi-wavelength field profiles before and after optimization;

  • a complete target run and a fresh forward validation of the best design.